1. Field of the Invention
This invention relates to the formation of integrated circuit structures. More particularly, this invention relates to a multiple step process for depositing a conformal film of uniform thickness on stepped surfaces of an integrated circuit surface.
2. Description of the Related Art
In the formation of integrated circuit structures of ever smaller dimensions, it has become important to form vias or contact openings with high aspect (height to width) ratios. Processes and apparatus have been developed to fill such vias or contact openings by sputtering without the formation of voids (by premature deposition on the upper surfaces of the opening) using a plasma beam having very little angular distribution so that the opening fills from the bottom up. A process and apparatus for such sputter deposition may be found in copending U.S. patent application Ser. No. 08/647,184, filed May 9, 1996 and assigned to the assignee of this invention, the subject matter of which is hereby incorporated by reference.
It has also become necessary to use filler materials for such vias or contact openings which require a liner on the bottom and sidewall surfaces of the via or contact opening which either act as a nucleation layer for the filler material or as a diffusion barrier to prevent the filler material from diffusing into the sidewall of the opening.
However, it is very difficult to form a barrier layer or film of uniform thickness on stepped surfaces such as the bottom and sidewalls of high aspect ratio vias or contact openings using a sputtering process. Nevertheless, at least in some circumstances, a sputter deposition is the desired form of deposition of the particular liner material. It would, therefore, be highly desirable to provide a process wherein a material of uniform thickness could be sputtered onto stepped surfaces on an integrated circuit structure such as, for example, to form a liner or barrier layer on the bottom and sidewall surfaces of a high aspect ratio via or contact opening.
In accordance with the invention, a multiple step process is used to sputter deposit a material of uniform thickness on stepped surfaces of an integrated circuit structure such as, for example, the bottom and sidewall surfaces of a high aspect ratio via or contact opening, or a narrow trench. During five separate deposition steps, one or more parameters comprising: the pressure in the deposition chamber, the DC power applied to the target, the RF power coupled to the plasma through the coil, and the RF bias on the pedestal holding the semiconductor substrate having sputtered material thereon, are varied to change the angular distribution of the beam of sputtered material to thereby provide a process resulting in a uniform deposition of material on the stepped surfaces such as the bottom and sidewalls of a high aspect ratio opening in a layer of an integrated circuit structure.
In a first deposition step, wherein material is sputter deposited at the bottom of the opening, the sputter deposition is carried out at high pressure using an RF source maintained at high power which is connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the pedestal supporting the substrate being deposited upon, and a low power DC bias is applied to the sputtering target.
In a second deposition step, the parameters of the first step are retained except that the high power RF bias on the pedestal holding the substrate is either reduced to a low power level at the commencement of the second step, or slowly reduced down to zero by the end of the second step, to thereby increase the angular distribution of the sputtering beam sufficiently to provide a deposition on the lowest quarter or quartile of the sidewall of the opening. In the third deposition step, the RF bias on the pedestal remains at zero (in an off position) and the pressure is now reduced to a medium pressure state, with the other two parameters of low power DC bias on the target and high RF power to the coil remaining the same, resulting in a further increase in the angular distribution of the sputtering beam and deposition on the second quartile of the sidewall of the opening, i.e., to complete the deposition on the lower one-half of the sidewall of the opening.
In the fourth deposition step, the pressure remains at a medium level, the RF bias applied to the pedestal remains at zero, and the DC bias power on the target remains low. However, in this step, the RF power coupled to the plasma through the coil is reduced to a low power level, resulting in a further increase in the angular distribution of the sputtering material and deposition on the sidewalls of the third quartile from the bottom of the opening. Finally, in a fifth deposition step, the last quartile of the sidewalls of the opening is deposited upon by lowering the pressure further to a low pressure level and applying a high power DC bias to the target, while maintaining the RF power to the coil at a low power level and with no RF bias applied to the pedestal. The end result of the five steps of the sputtering process of the invention is the desired deposition of material of uniform thickness on the bottom and sidewalls of the opening.